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Very Low Input Voltage 2-Phase Synchronous Step-down Controllers with Step-up Converter
POWER MANAGEMENT Description
The SC2441 is a high-frequency triple output switching regulator controller. It consists of a dual out-of-phase synchronous step-down PWM controller with high-current output gate drives and a 1.7A integrated step-up switching regulator. The dual-phase step-down controller of the SC2441 can be configured to provide two individually controlled and regulated outputs or a single output with shared current in each phase. The buck controller can operate from an input voltage of at least 4.72V or they can run off a supply generated locally with the integrated boost regulator. This makes the SC2441 ideally suited for applications where a low-voltage input (3.3V, 2.5V, or 1.8V) is to be stepped down for lower voltage logic yet the input is too low to drive power MOSFET's efficiently. The boost regulator can be used to provide a third auxiliary output while generating the bias for the buck controllers. Both the step-down controllers and the step-up regulator employ fixed frequency peak current-mode control for fast transient response. The master oscillator frequency can be programmed by the user. Individual soft-start and overload shutdown timer are employed in each step-down controller for hiccup overload protection. In single-output configuration, the channel 1 timer controls the soft-start and overload shutdown functions of both controllers.
SC2441
Features
2-Phase Synchronous step-down controllers 2-Phase Synchronous Continuous Conduction Mode For High Efficiency Step-down Converters Out of Phase Operation For Low Input Current Ripples Operates Up To 1MHz Per Channel Configurable Dual Outputs Or 2-Phase Single Output Operation with Peak Current Mode Control Excellent Current Sharing Between Phases Wide Input Voltage Range: 1.8V to 15V Duty Cycle Up to 90% 0.5V Feedback Voltages For Low-Voltage Outputs Precision 50mV Current-Limit Threshold Patented Combi-sense Technique for High SNR of Current-Sensing Individual Soft-Start, Overload Shutdown and Enable Step-up Regulator Wide Input Voltage Range: 1.8V to 15V Operates At Twice The Individual Channel Frequency Of The Buck Controllers 0.23V VCESAT Switch at 1A Fixed Frequency with Current-Mode Control Common Features External Synchronization Industrial Temperature Range
Applications
Low Voltage Distributed DC-DC Converters Telecommunication Power Supplies Servers and base stations
VIN VINGND
Typical Application Circuit
R12 D1 R14
+
C38
D2
VIN
C36 + C1 C2 R28 7 8 FB3 COMP3 PVIN BST2 GDH2 IN PH3 BST1 GDH1 L3 1 D3
VIN
C3
C18
VIN
Q1 R3
28 18
27 25 23 R4
+
C4
C17
VO1
C8 C25 R9
Q2 L2 C23 R6 R13 RCS+2 C21 R11
L1 C20 R5 C19 R10 D7 Q6
19
VO2
C24 + C15
VO1GND
+
R7 20
SC2441
GDL2 GDL1 PGND 2 22 24 26 4 5 11 12 C31 GND 6 3 17 SY NC SS1/EN1 SS2/EN2 Rosc VCC 9 10 21 R20 R8 Q7
D10
VO2GND
RCS+1
VPN2 CS2+ CS2FB2 COMP2
VPN1 CS1+ CS1FB1 COMP1
16 15
RCS-1 C27 R18 R17 C30
14 13
RCS-2 C28 R19
R16
C32
Figure 1
Revision: January 10, 2005
C33
U1
1
US patent 6,441,597
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SC2441
POWER MANAGEMENT Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Input Voltages Supply Voltage For Step-Dow n Controller High-Side Driver Supply Voltages FB1, FB2 Voltage COMP1, COMP2 Voltages CS1(+), CS1(-), CS2(+) and CS2(-) Voltages SY NC/SHDN Voltage ROSC Voltage SS1/EN1 AND SS2/EN2 Voltages Peak Gate Drive Current Peak VPN1 and VPN2 Output Currents FB3 Voltage COMP3 Voltage PH3 Voltage Ambient Temperature Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Storage Temperature Range Lead Temperature (Soldering) 10 sec
Symbol VIN , VPVIN VCC VBST1, VBST2 VFB1, VFB2 VCOMP1, VCOMP2 VCS1(+), VCS1(-), VCS2(+), VCS2(-) VS/S VROSC VSS1, VSS2 IGDH1, IGDH2, IGDL1, IGDL2 IVPN1, IVPN2 VFB3 VCOMP3 VPH3 TA JC JA TSTG TLEAD
Maximum Ratings -0.3 to 20 -0.3 to 20 -0.3 to 20 -0.3 to 20 -0.3 to 4.5 -0.3 to 20 -0.3 to 20 -0.3 to 5 -0.3 to 6 3 100 4 -0.3 to 2 -0.3 to 35 -40 to 85 13 84 -60 to 150 260
Units V V V V V V V V V A mA V V V C C/W C/W C C
Electrical Characteristics
Unless specified: VIN = 2V, VCC = VBST1 = VBST1 =8V, SYNC/SHDN =2V, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Undervoltage Lockout VCC Start Threshold VCC UVLO Threshold VCC Operating Current Channel 1 and 2 Error Amplifiers Feedback Voltage Feedback Pin Input Bias Current Amplifier Transconductance Open Loop Voltage Gain Amplifier Unity Gain Bandwidth Amplifier Output Sink Current Amplifier Output Source Current COMP Threshold for PWM Operation FB2 Voltage For 2-Phase Single Output Operation
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Symbol VCCTH VCCTL ICC
Conditions VCC Increasing VCC Decreasing VCC = 8V, VS/S = 2V VCC < VCCTL, VS/S = 2V VCC = 8V, VS/S = 0V VIN = 3V VCCTL < VCC < 10V -40C < TA < 85C
Min
Typ 4.65
Max 4.72 21 0.25 13
Units V V mA
4.34
4.45 14 0.15 10
VFB1, VFB2 IFB1, IFB2 GM1, GM2 ao1, ao2
0.487
0.496 -160 400 75
0.507 -400
V nA -1 dB MHz
(Note 1) VFB1, 2 = 1V, VCOMP1,2 = 2.5V VFB1, 2 = 0V, VCOMP1,2 = 2.5V VCS1(+) = VCS1(-) = 0 VCS2(+) = VCS2(-) = 0 -40C < TA < 85C 20 10 1.3 1.55
2
5 32 17 1.7 40 30 2.2
A A V V
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SC2441
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VIN = 2V, VCC = VBST1 = VBST1 =8V, SYNC/SHDN =2V, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Oscillator Step-dow n Channel Sw itching Frequency Maximum Duty Cycle Minimum Duty Cycle SY NC/SHDN Synchronizing Frequency SY NC/SHDN Input High Voltage SY NC/SHDN Input Low Voltage SY NC/SHDN Input Current Shutdow n Delay
Symbol fOSC1, fOSC2 DMAX1, DMAX2 DMIN1, DMIN2 VS/SH VS/SL IS/S
Conditions ROSC = 51.1k ROSC = 51.1k ROSC = 51.1k ROSC = 51.1k (Note 1)
Min 470 88
Typ 510 90
Max 550
Units KHz %
0 1.2 1.5 0.5 2
% MHz V V A s
VS/S = 0.2V VS/S = 2V (Note 1)
50 85
1 100
Current-Sense Amplifiers and Current-Limit Comparators Current Limit Threshold Current Limit Threshold Positive Current-Sense Input Bias Current Negative Current-Sense Input Bias Current Minimum PWM On-time Gate Drivers High-Side Gate Drive Peak Source Current High-Side Gate Drive Peak Sink Current Low -Side Gate Drive Peak Source Current Low -Side Gate Drive Peak Sink Current Gate Drive Rise Time Gate Drive Fall Time Low -side Gate Drive to High-side Gate Drive Non-overlapping Delay High-side Gate Drive to Low -side Gate Drive Non-overlapping Delay Soft-Start, Overload Shutoff and Enable Soft-Start Charging Current Soft-Start Voltage to Enable Overload Shutoff Overload Shutoff FB Threshold Soft-Start Discharge Current Soft-Start Voltage to Recover From Overload Shutoff ISS1, ISS2 VSSEN1, VSSEN2 VFBOL1, VFBOL2 ISS1(DIS), ISS2(DIS) VSSRCV1, VSSRCV2 VSS1 = VSS2 = 1.5V VSS1 and VSS2 Increasing VSS1, 2 = 3.8V FB1 and FB2 Decreasing VFB1 = VFB2 = 0.3V VSS1 = VSS2 = 3.8V VSS1 and VSS2 Decreasing 0.29 0.348 2.3 3.25 0.36 1.4 0.47 0.63 0.372 A V V A V (Note 1) (Note 1) (Note 1) (Note 1) CL = 3300pF CL = 3300pF CL = 0 CL = 0 2 2 2 2 30 30 74 62 A A A A ns ns ns ns VILIM1, VILIM2 VILIM1, VILIM2 ICS1(+), ICS2(+) ICS1(-), ICS2(-) VCC = 8V VCS1(-) = VCS2(-) = 0V VCC = 8V VCS1(-) = VCS2(-) = 5V VCS1(+) = VCS1(-) = 0 VCS2(-) = VCS2(-) = 0 VCS1(+) = VCS1(-) = 0 VCS2(+) = VCS2(-) = 0 TA = 25C, (Note 1) 40 40 48 46.5 -0.37 -0.32 180 56 56 -1 -1 mV mV A A ns
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SC2441
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VIN = 2V, VCC = VBST1 = VBST1 =8V, SYNC/SHDN =2V, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Gate Drive Disable SS/EN Voltage Gate Drive Enable SS/EN Voltage Virtual Phase Nodes Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Boost Converter VIN Start Threshold VIN UVLO Threshold Feedback Pin Bias Current Feedback Voltage Feedback Amplifier Transconductance Feedback Amplifier Open-Loop Gain Boost Converter Switching Frequency Maximum Switch Duty Cycle Boost Converter Switch Saturation Voltage Boost Switch Leakage Current Boost Switch Current Limit
Symbol
Conditions
Min 1.2
Typ
Max 0.5
Units V V
VVPN1,2H VVPN1,2L VVPN1,2H VVPN1,2L VINTH VINTL IFB3 V FB 3 GM3 a o3 fOSC3 DMAX3 VCESAT ILEAKAGE ILIMIT
IVPN1=0, IVPN2=0 IVPN1=0, IVPN2=0 IVPN1= IVPN2= -12mA IVPN1= IVPN2= 12mA VIN Increasing VIN Decreasing 1.55V < VIN < 16.5V -40C < TA < 85C
PVIN 0.05 20 PVIN 0.22 200 1.74 1.45 1.59 40 1.225 1.250 180 50 250 1.275 1.8
V mV V mV V V nA V -1 dB 1.1 86 0.23 0.35 5 MHz % V A A
ROSC = 51.1k ISW = 1A, TA = 25C V S W = 12V
0.94 82
1.7
2
Note 1: Guaranteed by design not tested in production.
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SC2441
POWER MANAGEMENT Pin Configurations
(TOP VIEW)
IN VPN2 SS1/EN1 CS1+ CS1SYNC/SHDN FB3 COMP3 GND ROSC FB1 COMP1 COMP2 FB2
Ordering Information
D evice SC 2441ITSTRT(1)(2) S C 2441E V B
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PVIN PH3 VPN1 BST1 PGND GDH1 GDL1 VCC GDL2 GDH2 BST2 SS2/EN2 CS2+ CS2-
P ackag e TSSOP-28
Temp. R ange( TA) -40 - 85C
Evaluati on Board
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for the TSSOP-28 package. (2) Lead free product.
(28-Pin TSSOP)
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SC2441
POWER MANAGEMENT Pin Descriptions
Pin 1 2 Pin N ame IN VPN2 Pin Function Power Supply Voltage for the Analog Secti on of the Boost C onverter. The Vi rtual Phase (Unloaded) Node of the Second Step-down C onverter. Used for "C ombi " current sense only. Thi s pi n i s left open when sensi ng current wi th a sense resi stor at the converter output. An external capaci tor ti ed to thi s pi n sets (i ) the soft-start ti me (i i ) output overload latch off ti me for step-down converter 1. Pulli ng thi s pi n below 0.5V shuts off the gate dri vers for the fi rst controller. The Non-i nverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down C ontroller 1. The Inverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down C ontroller 1. Normally ti ed to the output of the converter. Synchroni zati on and Shutdown Input. For normal operati on, ti e thi s pi n to a voltage above 1.5V. To shut-off both step-down controllers and the boost regulator, force thi s pi n to a voltage less than 0.5V. The master osci llator can be synchroni zed by dri vi ng thi s pi n wi th an external clock (external fCLK > frequency set wi th ROSC ). The boost converter runs at the external clock frequency whereas the step-down controllers operate at half the clock frequency. The Inverti ng Input of the Error Ampli fi er for the Boost C onverter. FB3 i s ti ed to an external resi sti ve di vi der for output3 voltage setti ng. The Error Ampli fi er Output of the Boost C onverter. Thi s pi n i s used for loop compensati on. Pulli ng thi s pi n below 0.4V di sables the step-up converter. Analog Si gnal Ground. An external resi stor connected from thi s pi n to GND sets the osci llator frequency. The Inverti ng Input of the Error Ampli fi er for the Step-down C ontroller 1. Ti e to an external resi sti ve di vi der between OUTPUT1 and the ground for output voltage sensi ng. The Error Ampli fi er Output for Step-down C ontroller 1. Thi s pi n i s used for loop compensati on. The Error Ampli fi er Output for Step-down C ontroller 2. Thi s pi n i s used for loop compensati on. The Inverti ng Input of the Error Ampli fi er for the Step-down C ontroller 2. Ti e to an external resi sti ve di vi der between output2 and the ground for output voltage sensi ng. Ti e to IN or VC C for two-phase si ngle output appli cati ons The Inverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down C ontroller 2. Normally ti ed to the output of the converter. The Non-i nverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down C ontroller 2 An external capaci tor ti ed to thi s pi n sets (i ) the soft-start ti me (i i ) output overload latch off ti me for step-down converter 2. Pulli ng thi s pi n below 0.5V shuts off the gate dri vers for the second controller. Leave open for two-phase si ngle output appli cati ons. Bootstrapped Supply for the Hi gh-si de Gate D ri ve 2. C onnect to a bootstrap capaci tor and an external di ode as descri bed i n appli cati on i nformati on. Gate D ri ve Output for the Hi gh-si de N-channel MOSFET of Output 2. Gate dri ve voltage swi ngs from ground to VBST2. Gate D ri ve Output for the Low-si de N-channel MOSFET of Output 2. Gate dri ve voltage swi ngs from ground to VC C .
3
SS1/EN1
4 5
C S 1+ C S 1-
6
SYNC /SHD N
7 8 9 10 11 12 13
FB 3 C OMP3 GND ROSC FB 1 C OMP1 C OMP2
14
FB 2
15 16
C S 2C S 2+
17
SS2/EN2
18 19 20
BST2 GD H2 GD L2
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SC2441
POWER MANAGEMENT Pin Descriptions
21 VCC Supply Voltage for Both Step-dow n Controllers and the Low -side Gate Drivers. The boost converter output is tied to VCC if VIN in not high enough to fully enhance the pow er MOSFET's and the boost converter provides an auxiliary supply voltage for the step-dow n controllers. Tie VCC to VIN if the boost converter is not needed. Gate Drive Output for the Low -side N-channel MOSFET of Output 1. Gate drive voltage sw ings from ground to VCC. Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage sw ings from ground to VBST1. Ground Supply of the High-side and the Low -side Gate Drivers of Both Step-dow n Controllers. It is also the emitter of the boost sw itch. Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an external diode as described in application information. The Virtual Phase (Unloaded) Node of the First Step-dow n Converter. Used for "Combi" current sense only. This pin is left open w hen sensing current w ith a sense resistor at the converter output. Boost Sw itch Collector. Connect to a boost inductor and a rectifying diode. Pow er Supply Voltage for the Boost Sw itch and the Virtual Phase Node Drivers.
22 23 24 25
GDL1 GDH1 PGND BST1
26 27 28
VPN1 PH3 PVIN
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SC2441
POWER MANAGEMENT Block Diagram
VIN UVLO 1.60/1.74V IN 1 PVIN CLK2 OSCILLATOR FREQUENCY CLK1 DIVIDER SLOPE COMP SHDN SHDN SLOPE2 28 0.5V 0.36V VCC 21 UVLO 4.45/4.65V BST1 25 GDH1 23 R S Q Non-Overlapping Conduction Control FAULT VPN1 26 GDL1 22
1.25V SYNC/SHDN 6 ROSC 10 COMP1 12 FB1 11 0.5V CLK
REFERENCE
-
+
EA1
SLOPE1
+
PWM1
CS1+ 4 CS15
+
-
ISEN1
+
+
+
Soft-Start And Overload Hiccup Control 1
OL DSBL PGND 24 SS1/EN1 3 B A Y SEL
50mV 1.25V
-
ILIM1 I
+
SEL ANALOG SWITCH CLK2
BST2 18 GDH2
COMP2 13 FB2 14 0.5V
-
19 EA2
+
SLOPE2
R S Q Non-Overlapping Conduction VCC Control FAULT
PVIN VPN2 2 GDL2 20
+
PWM2
CS2+ 16 CS215
+
-
ISEN2
+
+
+
Soft-Start And Overload Hiccup Control 2
OL DSBL SS2/EN2 17
GND 9
50mV
-
ILIM2 I
Step-down Controllers Functional Diagram
Figure 2
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SC2441
POWER MANAGEMENT Block Diagram
COMP3 8 FB3 7 1.25V CLK PH3 27
+
EA3
-
R S Q
+
PWM3
ILIM3 SLOPE COMP
+
-
14mV
7m
+
+
+
ISEN3
-
24
Step-up Converter Functional Diagram
Figure 3
PGND
FB 0.36V SS/EN
+
2
S Q R 0.47V/3.25V OL
DSBL FAULT 0.6V/0.9V
3
Details of the Soft-start and Overload Hiccup Control Circuit
Figure 4
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SC2441
POWER MANAGEMENT Typical Performance Characteristics
FB1 AND FB2 VOLTAGES vs TEMPERATURE 0.5 V IN = 2V 0.498 VOLTAGE (V) V CC = 5V 1.3 VIN START AND UVLO THRESHOLD VOLTAGES vs TEMPERATURE 2
FB3 VOLTAGE vs TEMPERATURE
1.28 VOLTAGE (V) VOLTAGES (V)
1.9
0.496
1.26
1.8 VIN START 1.7 VIN UVLO
0.494
1.24
0.492
1.22
1.6
0.49 -50 -25 0 25 50 75 100 TEMPERATURE (C)
1.2 -50 -25 0 25 50 75 100 TEMPERATURE (C)
1.5 -50 -25 0 25 50 75 100 TEMPERATURE (C)
VCC START AND UVLO THRESHOLD VOLTAGES vs TEMPERATURE 5 520 515 4.8 FREQUENCY (KHz) VCC START VOLTAGES (V) 4.6 VCC UVLO 4.4 510 505 500 495 490 485 4 -50 -25 0 25 50 75 100 TEMPERATURE (C) 480 -50
STEP-DOWN CHANNEL SWITCHING FREQUENCY vs TEMPERATURE ROSC = 51.1K
STEP-UP CONVERTER SWITCHING FREQUENCY vs TEMPERATURE 1050 1040 1030 FREQUENCY (KHz) 1020 1010 1000 990 980 970 960 950 ROSC = 51.1K
4.2
-25
0
25
50
75
100
-50
-25
TEMPERATURE (C)
0 25 50 TEMPERATURE (C)
75
100
MAXIMUM DUTY- CYCLE OF STEP-DOWN CHANNEL vs TEMPERATURE 95 ROSC = 51.1K 93 DUTY CYCLE (%) DUTY CYCLE (%)
STEP-UP SWITCH MAXIMUM DUTY- CYCLE vs TEMPERATURE 90 ROSC = 51.1K 88 VOLTAGES (mV) 48 50
STEP-DOWN CONTROLLER CURRENT-LIMIT THRESHOLD vs TEMPERATURE CS(-) = 0
91
86
46
CS(-) = 5V
89
84
44
87
82
42 VCC = 8V
85 -50 -25 0 25 50 75 100 TEMPERATURE (C)
80 -50 -25 0 25 50 75 100 TEMPERATURE (C)
40 -50 -25 0 25 50 75 100 TEMPERATURE (C)
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SC2441
POWER MANAGEMENT Operation
Overview The SC2441 is a constant frequency triple-output switching regulator especially designed for operating from input voltages as low as 1.8V. It consists of two currentmode step-down switch-mode PWM controllers driving all N-channel MOSFET's and a 1.7A step-up current-mode controller with integrated 1.7A power switch. A low voltage input (3.3V, 2.5V or 1.8V) can be stepped up to 5V-10V locally using the boost regulator to provide sufficient gate drives for the step-down converters. The boost converter can also be used to generate a third output. The two step-down channels of the SC2441 operate at 180 degrees out of phase from each other. Since input currents are interleaved in a two-phase converter, input ripple current is lower and smaller input capacitor can be used for filtering. The step-down controllers of the SC2441 operate in synchronous continuous-conduction mode. They can be configured either as two independent step-down controllers producing two separate outputs or as a dualphase single-output controller by tying the FB2 pin to VCC. In single output operation, the channel-one error amplifier controls both channels and the channel-two error amplifier is disabled. Soft-start and overload hiccup of both channels is also synchronized to channel one. Frequency Setting and Synchronization The step-up regulator in the SC2441 runs at twice the frequency of step-down controllers. Each step-down controller runs at one-half of the oscillator frequency and is 180 degrees out of phase from the other step-down controller. The switching frequency of the step-up regulator is the oscillator frequency and can be set with an external resistor from the ROSC pin to the ground. The boost regulator and the step-down controllers are capable of operating up to 2 MHz and 1 MHz respectively. It is necessary to consider the operating duty-ratio range before deciding the switching frequency. See Applications Information section for more details. When synchronized externally, the applied clock frequency (hence switching frequency of the step-up converter) should be twice the individual phase frequency of the step-down controllers. The synchronizing clock frequency
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should also be between 1-1.33 times the set free-running frequency. If not synchronized, the SYNC/SHDN pin should be tied to the input. Pulling the SYNC/SHDN pin below 0.5V shuts off the SC2441 after 85s time delay. Control Loop The step-down controllers and the boost regulator in the SC2441 use peak current-mode control for fast transient response, ease of compensation and current sharing in single output operation. The low-side MOSFET of each step-down channel is turned off at the falling-edge of the phase clock. After a brief non-overlapping conduction interval of 74ns, the high-side MOSFET is turned on. The phase inductor current ramps up. When the sensed inductor current reaches the threshold determined by the error amplifier output and ramp compensation, the high-side MOSFET is turned off. After a non-overlapping delay of 62ns, the low-side MOSFET is turned on. The supply voltages for the high-side gate drivers are obtained from two diode-capacitor bootstrap circuits. If the bootstrap capacitor is charged from VCC, then the high-side gate drive voltage will swing from approximately 2VCC to the ground. The outputs of the low-side gate drivers swing from VCC to the ground. All three converters in the SC2441 have internal rampcompensation to prevent sub-harmonic oscillation when operating above 50% duty cycle. The internal compensating ramp is designed for an inductor ripplecurrent of between 1/4 to 1/3 of the maximum inductor current and the peak-to-peak current-sense voltage (CSPCSN of the step-down controllers) of between 1/4 to 1/3 of the current-limit threshold (50mV). The current-limits of all three converters are unaffected by the compensation ramps. Current-Sensing Since the inductor current ramp is used as the modulating ramp in current-mode control, the inductor current needs to be sensed. There are two current sensing methods for the step-down controllers. Since the maximum currentsense voltage (CSP-CSN) is only 50mV, a precision sense resistor in series with the inductor can be used at the output without resulting in excessive power dissipation.
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SC2441
POWER MANAGEMENT Operation (Cont.)
Although accurate and far easier to lay out than highside resistor sensing, a pair of precision sense resistors adds cost to the converter. The SC2441 has provision to reconstruct a differential voltage proportional to the inductor current at the output of the converter. The voltage to current ratio or the equivalent sense resistance Req is a combination of high-side and low-side MOSFET RDS(ON) 's and the inductor series resistance (hence the name "combi-sense"). The SC2441 provides the virtual phase voltages VPN1 and VPN2 (these are unloaded versions of their respective phase voltages) for current sensing. This method does not require precision sense resistor. It is cheaper to implement but is less accurate than resistor current sensing. Since the sensed voltage is developed at the output of the step-down converter, it is less prone to switching transient spikes. This method will be described in more details in the Applications Information section. Boost switch current is sensed with an integrated sense resistor with a current-limit of 1.7A. Error Amplifiers All error amplifiers in the SC2441 are transconductance amplifiers. Converters are compensated with series RC network from the COMP pins to the ground. An additional small parallel capacitor may be required for stability. In closed loop operation, the step-down error amplifiers output range from 1.7V to 3.5V. There is no control (highside) gate drive until the COMP voltage exceeds 1.6V. Both non-inverting inputs of the feedback amplifiers are tied to an internal 0.5V voltage reference. The error amplifier of the step-up converter has 1.25V as its reference voltage. Its output voltage ranges from 0.8V to 1.35V in closed-loop operation. Current-Limit The maximum current sense voltage of +50mV is the cycle-by-cycle peak current limit when the load is drawing current from the converter. Soft-Start and Overload Protection The undervoltage lockout circuit discharges the SS/EN capacitors. After VCC rises above 4.65V, the SS/EN capacitors are slowly charged by internal 2.3A current sources. With internal PNP transistors, the SS/EN voltages clamp the error amplifier outputs. When the error amplifier output rises to 1.7V, the high-side MOSFET starts to switch. As the SS/EN capacitor continues to charge, the COMP voltage follows. The converter gradually delivers increasing power to the output. The inductor current follows the COMP voltage envelope until the output goes into regulation. The SS/EN clamp on COMP is released. After the SS/EN capacitor is charged above 3.25V (high enough for the error amplifier to provide full load current), the overload detection circuit is activated. If the output voltage falls below 70% of its set value, an overload latch will be set and both the top and the bottom MOSFET's will be turned off. The SS/EN capacitor is slowly discharged with an internal 1.4A current sink. The overload latch is reset when the SS/EN capacitor is discharged below 0.47V. The SS/EN capacitor is then recharged with the 2.3A current source and the converter undergoes soft-start. If overload persists, the step-down converters will undergo repetitive shutdown and restart (hiccup). Soft-start process should be slow enough to allow the output to reach 70% of its final value before the SS/ EN capacitor is charged above 3.25V (see Figure 4). If the output is short-circuited, the inductor current will not increase indefinitely between the time the inductor current reaching its current limit and shutdown. This is due to cycle skipping reduces the actual operating frequency. The SS/EN pin can also be used as the enable input for that channel. Both the high-side and the low-side MOSFET's will be turned off if the SS/EN pin is pulled below 0.5V.
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SC2441
POWER MANAGEMENT Applications Information
The SC2441 consists of two current-mode synchronous buck controllers and an auxiliary boost converter. The SC2441 can be used to generate 1) two independent step-down outputs or 2) dual phase single output with current sharing and 3) a step-up output The application information using SC2441 for the control of step-down and step-up converters are described below. Step-down Converter Specifications of a step-down converter are given by the followings Input voltage range: Vin [ Vin,min , Vin,max ] Input voltage ripple (peak-to-peak): Vin Output voltage: Vo Output voltage accuracy: Output voltage ripple (peak-to-peak): Vo Nominal output (load) current: Io Maximum output current limit: Io,max Output (load) current transient slew rate: dIo (A/s) Circuit efficiency: . Based on these converter specifications, selection criteria and design procedures for the following components are described. 1) output inductor (L) type and value, 2) output capacitor (Co) type and value, 3) input capacitor (Cin) type and value, 4) power switch MOSFET's, 5) current sensing and limiting circuitry, 6) voltage sensing circuitry, 7) loop compensation circuitry. To illustrate the design process, the following example is used: Vin=3.3V, Vo=1.2V, Io=4A, fs=500kHz. Operating Frequency (fs) The switching frequency in the SC2441 is userprogrammable. The advantages of constant frequency operation are simple passive component selection and fast transient response with simple frequency compensation. Before setting the operating frequency, the following tradeoffs should be considered. 1) passive component sizes 2) converter efficiency 3) EMI 4) Minimum switch on time and 5) Maximum duty ratio For a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas MOSFET's/Diodes switching losses are proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues are also to be considered. The frequency bands for signal transmission should be avoided because of EM interference. Minimum Switch On Time Limitation In both step-down controllers, the falling edge of the clock turns on the top MOSFET. The inductor current ramps up so does the sensed voltage. After the sensed voltage crosses a threshold determined by the error amplifier output, the top MOSFET is turned off. The propagation delay time from the turn-on of the controlling FET to its turn-off is the minimum switch on time. The SC2441 has a minimum on time of about 180ns at room temperature. This is the shortest on interval of the controlling FET. The controller either does not turn on the top MOSFET at all or turns it on for at least 180ns. For a synchronous step-down converter, the operating duty cycle is V /V . So the required on time for the top o IN MOSFET is V /(V fS). If the frequency is set such that o IN the required pulse width is less than 180ns, then the converter will start skipping cycles. Due to minimum on time limitation, simultaneously operating at very high switching frequency and very short duty cycle is not practical. If the input voltage is 3.3V and the operating frequency is 1MHz, the lowest output voltage will be 0.6V. There will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the SC2441. For ease of control, we recommend the required pulse width to be at least 1.5 times the minimum on time. Maximum Duty-cycle Consideration When operating at 500KHz, the maximum top MOSFET on duty-cycle is 90%. The top MOSFET therefore turns off for at least 200ns every cycle regardless of the switching frequency. This places an upper bound on the voltage
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2005 Semtech Corp.
SC2441
POWER MANAGEMENT Applications Information (Cont.)
conversion ratio at a given switching frequency. If the desired output voltage requires high operating duty-cycle, then operating frequency will have to be lowered to allow modulating headroom. Setting the Step-down Channel Frequency The switching frequency of both step-down controllers is set with an external resistor from Pin 10 to the ground. The set frequency is inversely proportional to the resistor value (Figure 5).
L= Vo (1 - D) . Io fs
The peak current in the inductor becomes (1+/2)*Io and the RMS current is
IL,rms = Io 1 + 2 . 12
800 700 600 fs (kHz) 500 400 300 200 100 0 0 50 100 150 200 250 Rosc (k Ohm)
The followings are to be considered when choosing inductors. a) Inductor core material: For high efficiency applications above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitive-applications below 350KHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The designer can choose the adjacent (larger) standard inductance value. The inductance varies with temperature and DC current. It is a good engineering practice to re-evaluate the resultant current ripple at the rated DC output current. c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. Output Capacitor (Co) and Vout Ripple
Figure 5. Step-down Channel Free-running frequency vs. ROSC. Inductor (L) and Ripple Current Both step-down controllers in the SC2441 operate in synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. Conversely smaller inductors results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. Assuming that the inductor current ripple (peak-to-peak) is *Io, the inductance will then be
2005 Semtech Corp.
The output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure 6).
Co
Lesl
Resr
Figure 6. Co equivalent circuit If the current through the branch is ib(t), the voltage across the terminals will then be
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
di ( t ) 1 v o ( t ) = Vo + ib ( t )dt + L esl b + R esr ib ( t ). Co 0 dt
t
Io 23
.
This basic equation illustrates the effects of ESR, ESL and Co on the output voltage. The first term is the DC voltage across Co at time t=0. The second term is the ripple-voltage caused by the inductor ripple-current. The third term is the voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last three terms. Since the inductor current is a triangular waveform with peak-to-peak value *Io, the ripple-voltage caused by inductor current ripples is
v C Io . 8Co fs Io D
Usually it is necessary to have several capacitors of the same type in parallel to satisfy the ESR requirement. The voltage ripple cause by the capacitor charge/discharge should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy
Co > 10 . 2fsR esr
The ripple-voltage due to ESL is
v ESL = L esl fs
In many application circuits, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors to further reduce ESR and improve high frequency decoupling. Since the capacitances and the ESR's of ceramic and aluminum capacitors are different, the following remarks are made to clarify some practical issues. Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. For example, if a 10F, 4m ceramic capacitor is connected in parallel with 2x1500F, 90m electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100F, 2m ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. When two 100F, 2m ceramic capacitors are used, the current ratio increases to 8.3. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESR's either. Instead they should be calculated using the following formulae.
C eq () := (R1a + R1b )2 2C1a C1b + (C1a + C1b )2 (R1a C1a + R1b C1b )2 C1a C1b + (C1a + C1b )
2 2 2 2
and the ESR ripple-voltage is
v ESR = R esr Io .
Aluminum capacitors (e.g. electrolytic, solid OS-CON, POSCAP, tantalum) have high capacitances and low ESL's. The ESR has the dominant effect on the output ripple voltage. It is therefore very important to minimize the ESR. When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To keep the steady state output ripple-voltage < Vo, the ESR should satisfy
R esr1 < Vo . Io
To limit the dynamic output voltage overshoot/undershoot within (say 3%) of the steady state output voltage) under 0 to full load current swing, the ESR value should be
R esr 2 Vo < . Io
The required ESR value of the output capacitors should be Resr = min{Resr1,Resr2 }. In the aluminum capacitor selection, the working voltage rating is normally suggested to be greater than 1.5Vo. The allowable current ripple (RMS) should be greater than
2005 Semtech Corp.
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
R eq () := R1aR1b (R1a + R1b )2C1a C1b + (R1b C1b + R1a C1a ) (R1a + R1b )2 2 C1a C1b + (C1a + C1b )2
2 2 2 2 2 2
In Figure 8 the DC input voltage source has an internal impedance Rin and the input capacitor Cin has an ESR denoted as Resr. MOSFET and input capacitor current waveforms, ESR voltage ripple and input voltage ripple are shown in Figure 9.
where R 1a and C 1a are the ESR and capacitance of electrolytic capacitors, and R1b and C1b are the ESR and capacitance of the ceramic capacitors respectively (Figure 7).
C1a
C1b
Ceq
R1a
R1b
Req
Figure 7. Equivalent RC branch. Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and Req = 1/2 R1 and Ceq = 2C1. Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 8.
Figure 9. Typical waveforms at the input of a buck converter. It can be seen that the current in the input capacitor pulses with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the MOSFET's on the PC board to reduce trace inductances around the pulse current loop. The RMS value of the capacitor current is approximately
ICin = Io D[(1 + 2 D D )(1 - )2 + 2 (1 - D) ]. 12
The power losses at the input capacitors is then PCin = ICin2Resr. For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10oC of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is
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Figure 8. Buck converter input model
2005 Semtech Corp.
SC2441
POWER MANAGEMENT Applications Information (Cont.)
v ESR = R esr (1 + )Io . 2
If D1>0.5 and D2 > 0.5, then
ICin (D1 + D 2 - 1)(Io1 + Io 2 )2 + (1 - D 2 )Io1 + (1 - D1 )Io2 .
2 2
The peak-to-peak input voltage ripple due to the capacitor is
v C DIo . Cin fs
Power MOSFET Selection and Gate Drive Main considerations in selecting the MOSFET's are power dissipation, cost and packaging. Switching losses and conduction losses of the MOSFET's are directly related to the total gate charge (Cg) and channel on-resistance (Rds(on)). In order to judge the performance of MOSFET's, the product of the total gate charge and on-resistance is used as a figure of merit (FOM). Transistors with the same FOM follow the same curve in Figure 10.
From these two expressions, CIN can be found to meet the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2441 operate at 180 degrees from each other. If both step-down channels in the SC2441 are connected in parallel, both the input and the output RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When converter outputs are connected in parallel and interleaved, smaller inductors and capacitors can be used for each channel. The total output ripple-voltage remains unchanged. Smaller inductors speeds up output load transient. When two channels with a common input are interleaved, the total DC input current is simply the sum of the individual DC input currents. The combined input current waveform depends on duty ratio and the output current waveform. Assuming that the output current ripple is small, the following formula can be used to estimate the RMS value of the ripple current in the input capacitor. Let the duty ratios and output currents of Channel 1 and Channel 2 be D1, D2 and Io1, Io2 respectively. If D1<0.5 and D2<0.5, then
ICin D1Io1 + D 2Io2 .
2 2
50 Gate Charge (nC) 40 Cg( 100 , Rds) Cg( 200 , Rds) Cg( 500 , Rds) 20
1
0
0 1
5
10
15
20 20
FOM:100*10^{-12} FOM:200*10^{-12} FOM:500*10^{-12}
Rds On-resistance (mOhm)
Figure 10. Figure of merit curves. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss or both. It may be difficult to find MOSFET's with both low Cg and low Rds(on. Usually a trade-off between Rds(on and Cg has to be made. MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss dominates for a particular MOSFET. For synchronous buck converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low duty cycle. The bottom switch conducts at high duty cycle but switches at near zero voltage. For such applications, MOSFET's with low Cg are used for the top switch and MOSFET's with low Rds(on) are used for the bottom switch.
If D1>0.5 and (D1-0.5) < D2<0.5, then
ICin 0.5Io1 + (D1 - 0.5)(Io1 + Io 2 )2 + (D 2 - D1 + 0.5)Io 2 .
2 2
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
ICin 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 - D 2 - 0.5)Io 2 .
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2 2
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
The losses in power MOSFET's consist of a) conduction loss due to the channel resistance Rds(on), b) switching loss due to the switch rise time tr and fall time tf and c) the gate loss due to the gate resistance RG. Top Switch: The RMS value of the top switch current is
IQ1,rms = Io D(1 +
2 12
).
In Figure 11, Qgs1 is the gate charge needed to bring the gate-to-source voltage Vgs to the threshold Vgs_th, Qgs2 is the additional gate charge required for the switch current to reach its full-scale value Ids and . Qgd is the charge needed to charge gate-to-drain (Miller) capacitance when Vds is falling. Switching losses occur during the time interval [t1, t3]. Defining tr = t3-t1. tr can be approximated as
tr = (Q gs 2 + Q gd )R gt Vcc - Vgsp .
Its conduction loss is then Ptc = IQ1,rms2 Rds(on). Rds(on) varies with temperature and gate-source voltage. Curves showing R ds(on) variations can be found in manufacturers' data sheet. From the Si7882DP datasheet, Rds(on) is less than 4.5m when Vgs is greater than 5V. However Rds(on) increases by nearly 40% as the junction temperature increases from 25C to 125C. The switching losses can be estimated using the simple formula
1 Pts = 2 ( t r + t f )(1 + 2 )Io Vin f s .
where Rgt is the total resistance from the driver supply rail to the gate of the MOSFET. It includes the gate driver internal impedance R gi, external resistance Rge and the gate resistance Rg within the MOSFET i.e. Rgt = Rgi+Rge+Rg. Vgsp is the Miller plateau voltage shown in Figure 11. Similarly an approximate expression for tf is
tf = (Q gs 2 + Q gd )R gt Vgsp .
where tr is the rise time and tf is the fall time of the switching process. Different manufactures have different definitions and test conditions for t and t . To clarify these, we sketch r f the typical MOSFET switching characteristics under clamped inductive mode in Figure 11.
Only a portion of the total losses Pg = QgVccfs is dissipated in the MOSFET package. Here Qg is the total gate charge specified in the datasheet. The power dissipated within the MOSFET package is
Ptg = Rg R gt Q g Vcc fs .
The total power loss of the top switch is then Pt = Ptc+Pts+Ptg. If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction loss is inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design.
charge
Figure 11. MOSFET switching characteristics
Bottom Switch: The RMS current in bottom switch can be shown to be
IQ 2,rms = Io (1 - D)(1 +
2 12
).
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2005 Semtech Corp.
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
The conduction loss is then Pbc=IQ2,rms2 Rds(on), where Rds(on) is the channel resistance of bottom MOSFET. If the input voltage to output voltage ratio is high (e.g. Vin=12V, Vo=1.5V), the duty ratio D will be small. Since the bottom switch conducts with duty ratio (1-D), the corresponding conduction losses can be quite high. Due to non-overlapping conduction between the top and the bottom MOSFET's, the internal body diode or the external Schottky diode across the drain and source terminals always conducts prior to the turn on of the bottom MOSFET. The bottom MOSFET switches on with only a diode voltage between its drain and source terminals. The switching loss
1 Pbs = 2 ( t r + t f )(1 + 2 )Io Vd fs
Using low gate charge MOSFET's reduces switching loss. It is possible to trade driver IC losses for MOSFET switching losses by adjusting the gate resistance. Lower gate resistance results in higher gate driving current and faster MOSFET switching. However the driver incurs higher losses. Conversely higher gate drive resistance limits the gate drive current, thus lowering the driver dissipation. MOSFET switching loss is higher. To prevent shoot-through between the top and the bottom MOSFET's during commutation, one MOSFET should be completely turned off before the other is turned on. In the SC2441 the top and the bottom gate drive pulses are made non-overlapping. When not driving any load, the nonoverlapping commutation intervals from the top to the bottom and from the bottom to the top gate drives are set at 62ns and 74ns respectively. If MOSFET's are driven from the SC2441, the non-overlapping commutation times will decrease due to finite gate-source voltage rise and fall times. The gate-source voltage waveforms of the MOSFET's should not overlap above their respective thresholds when driven from the SC2441. Use of low gate charge MOSFET's reduces transition times and the tendency of shoot-through. The combined rise and fall times during both commutations should be less than the preset non-overlapping intervals Current Sensing (Combi-Sense) Inductor current sensing is required for the current-mode control. Although the inductor current can be sensed with a precision resistor in series with the inductor, a novel (US patent 6,441,597) lossless combi-sense technique can also be used in the SC2441. This Semtech proprietary technique has the following advantages 1) lossless current sensing 2) higher signal-to-noise ratio and 3) preventing thermal run-away. The basic arrangement of the combi-sense is shown in Figure 12. In Figure 12 RL is the equivalent series resistance of the output inductor. Rs and Cs form a RC network for inductor current sensing. This branch is driven from a small totem pole driver (Q3 and Q4) within the SC2441. The base driving signals Vbe3 and Vbe4
is negligible due to near zero-voltage switching. The gate loss is estimated as
Pbg = Rg R gt Q g Vcc fs .
The total bottom switch loss is then Pb=Pbc+Pbs+Pbg. Once the power losses Ploss for the top (Pt) and bottom (Pb) MOSFET's are known, thermal and package design at component and system level should be done to verify that the maximum die junction temperature (Tj,max, usually 125oC) is not exceeded under the worst-case conditions. The equivalent thermal impedance from junction to ambient (ja) should satisfy
ja Tj,max - Ta,max Ploss .
ja depends on the die to substrate bonding, packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area and the air flow condition (free or forced convection). Actual temperature measurement of the prototype should be carried out to verify the thermal design. Integrated Power MOSFET Drivers There are four internal MOSFET drivers in step-down section of the SC2441 for driving all the MOSFET's in a dual-channel step-down converter.
2005 Semtech Corp.
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
Vin
Q1 Vgs1 i L (t ) PN C in Rs Q2 Vgs2 v C (t ) Cs L RL
Vin
PN
iL(t)
L Rs
RL Cs
Vo
C ou t R l o ad
C
in
Rds2
VP N vC (t)
Vo
C ou t
Rload
Vbe 3 VP N Vbe 4
Q3
Q4
Figure 13. b) Equivalent sub-circuit.
Figure 12. The basic structure of combi-sense. follow the gate drive signals Vgs1 and Vgs2 respectively with minimal delay. The transition edges at the Virtual Phase Node (VPN) therefore matches closely to those of the Phase Node (PN). When Q1/Q3 are on and Q2/Q4 are off, the circuit in Figure 12 is reduced to that of Figure 13 a). Here Rds1 is the onresistance of the top MOSFET. The branches {(Rds1+RL), L} and {Rs, CS}, are in parallel. The DC voltage across L and the DC current through CS are both zero. There is no DC voltage across Rs either. Therefore on average, the voltage drop (Rds1+RL)Io equals VCs. The DC inductor current can be sensed from VCs if (Rds1+RL) is known. When Q1/Q3 are off and Q2/Q4 are on, the equivalent circuit of Figure 12 reduces to the sub-circuit in Figure 13b). Here Rds2 is the channel resistance of the bottom MOSFET. In this case, the branch {Rs, Cs} is in parallel with {(Rds2+RL), L} and VCs=(Rds2+RL)Io. Averaging over one switching cycle, or
VCs=[D(Rds1+RL)+(1-D)(Rds2+RL)]Io
VCs=[D Rds1+(1-D)Rds2+RL]Io:=ReqIo. The DC voltage across VCs is independent of L, Rs and Cs. If only the average load current is needed (as in average current-mode control), this current sensing method will be sufficient without any additional time-constant matching constraint. In peak current-mode control, the voltage ripple on Cs is used as the modulating ramp. The VCs peak-to-peak amplitude (denoted as VCs) directly affects the signalto-noise ratio of the PWM operation. Small VCs leads to lower signal-to-noise ratio and more jittery operation. Large VCs leads to more circuit (power stage) sensitive operation. A good compromise is to make VCs~ReqIo. The above condition holds if the following time-constants are made equal.
L R sC s . R eq
Vin
Rds1 iL(t) PN Cin VPN vC(t) Rs Cs L RL
Vo
Cout Rload
If Rds1=Rds2, then Req = Rds1+ RL. For example, in the application circuit, L=1.3H, RL=1.56m and Rds1=Rds2=8m , the time constant RsCs should be set as 136s. If Cs=33nF, then Rs=4.12k.
Figure 13. a) Equivalent sub-circuit.
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
Setting the Current Limit When the voltage difference between CS1+(CS2+) and CS1- (CS2-) exceeds 50 mV, the top MOSFET will be turned OFF and the bottom MOSFET will be turned ON to limit the output inductor current. In the circuit of Figure 12, the converter output current limit is
ILMcp = 50mV . R eq
Rs=11.8k and Rs1=6.36k. b) The required current limit ILM is less than ILMcp. Rs1 is deleted from Figure 14. Rs is given by
R sC s = L , R eq
Rs3 is obtained from
ILMR eq + Rs VO = 50mV, R s3 R s 3R s . R s3 - R s
In the application circuit, Req = 9.56m so ILM = 5.23A. In other applications, different current limits may be required. The circuit in Figure 14 allows the user to set current-limit different from 50mV/Req.
Lastly Rs2 is computed from
R s2 =
Vin
Q1 V gs1 iL(t) PN Cin Rs Q2 V gs2 vC(t) Rs 1 L RL
If the current limit is to be set to ILM=2.5A with Vo=1.2V and Cs=33nF in the same example, then Rs=4.12 k, Rs3=190 k and Rs2=4.21 k. Remark 3: If the current limit ILM is lower than ILMcp, the circuit designer will have the option to use MOSFET's with higher Rds(ON) to reduce the cost. As a result, Req is increased and ILMcp is reduced. Although the use of low-cost MOSFET's is always preferred, the current-limit setting technique described above allows quick adjustment on a well-tested prototype without the need to replace the power MOSFET's. Over Current Protection and Hiccup Mode
Rs 2 R s3
Vo
Cs C out Rload
V be3 VP N V be4
Q3
Q4
+1 IS N E -2
Figure 14. Circuit for setting current-limit different from 50mV/Req a) The required current limit ILM is higher than ILMcp. Rs3 is deleted from Figure 14. Rs2 is given by
R s 2C s = L , R eq
Rs is obtained from
ILMR eq R s2 = 50mV, Rs R s 2R s . R s - R s2
During start-up, the capacitor from the SS/EN pin to ground functions as a soft-start capacitor. After the converter starts and enters regulation, the same capacitor operates as overload shutoff timing capacitor. As the load current increases, the cycle-by-cycle current-limit comparator will first limit the inductor current. Further increase in loading will cause the output voltage (hence the feedback voltage) to fall. If the feedback voltage falls to less than 70% of the normal, the controller will shut off both the top and the bottom MOSFET's. Meanwhile an internal current source (1.4A) discharges the soft start capacitor C 32(C 33 ) connected to the SS/EN pin. When the capacitor is discharged to 0.47V, a 2.3A current source recharges the SS/EN capacitor and the controller re-initiates soft-start. If the overload persists, the controller will shut down the converter as the soft start capacitor voltage exceeds 3.25V. The converter will repeatedly start and shut off until it is no longer overloaded. This hiccup mode of overload protection is a
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Rs1 is then computed from
R s1 =
If the current limit is to be set to ILM=15A in the example given in last section with Cs=33nF, then Rs2=4.12k,
2005 Semtech Corp.
SC2441
POWER MANAGEMENT Applications Information (Cont.)
form of foldback current limiting. The following calculations estimate the average inductor current when the converter output is shorted to the ground. a) The time taken to discharge the capacitor from 3.25V to 0.47V is resistance may not be available as a standard value resistor. As a result, there will be a set error in the converter output voltage. This non-random error is caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. The following table lists a few standard resistor combinations for realizing some commonly used output voltages.
Vo (V) (1- h)/h 0.6 0.2 0.9 0.8 806 1K 1.2 1.4 1.4K 1K 1.5 2 2K 1K 1.8 2.6 2.5 4 3.3 5.6
t ssf
(3.25 - 0.47)V . = C32 1.4A
If C32 = 0.1F, tssf will then be 200ms. b) The soft-start time from 0.47V to 3.25V is
t ssr = C 32 ( 3 .25 - 0 . 47 ) V . 2 .3 A
Ro1 (Ohm) 200 Ro2 (Ohm) 1K
2.61K 4.02K 5.62K 1K 1K 1K
If C32 = 0.1F, tssr will then be 121ms. Note that during soft-start, the converter only starts switching when the voltage at SS/EN exceeds 1.3V. c) The effective start-up time is
t sso = C32 (3.25 - 1.3)V . 2.3A
Only the voltages in boldface can be precisely set with standard 1% resistors. The input bias current of the error amplifier also causes an error in the output voltage. The inverting input bias currents of error amplifiers 1 and 2 are -160nA and - 260nA respectively. Since the non-inverting input is biased to 0.5V, the percentage error in the second output voltage will be -100% * (0.26A) * R R /[0.5 * (R +R )]. To o1 o2 o1 o2 keep this error below 0.2%, R < 4k. o2 Loop Compensation The SC2441 uses current-mode control for both step-down channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the complex high-Q poles of the output LC networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This polesplitting property of current-mode control greatly simplifies loop compensation. The inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper than the inductor current down-slope. For stable operation above 50% duty-cycle, a compensation ramp is added to the
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The average inductor current is then
ILeff = ILMcp
t sso . t ssf + t ssr
I Leff = 0.27I LMcp and is independent of the soft start capacitance. The converter will not overheat in hiccup. Setting the Output Voltage The non-inverting inputs of the error amplifiers are internally biased to 0.5V voltage reference. A simple voltage divider (Ro1 at top and Ro2 at bottom) sets the converter output voltage. Ro2 can be expressed as a function of the voltage feedback gain h=0.5/Vo and Ro1
Ro2 = h R o1. 1- h
Once either Ro1 or Ro2 is chosen, the other can be calculated for the desired output voltage Vo. Since the number of standard resistance values is limited, the calculated
2005 Semtech Corp.
SC2441
POWER MANAGEMENT Applications Information (Cont.)
sensed-current. In the SC2441 the compensation ramp is made duty-ratio dependent. The compensation ramp is approximately
Iramp = De
1.1D
For the rated output current Io, the first-order gain k is determined as
k= Io . Vc
* 4.8A.
The incremental slope of such current ramp is then
Se = (1 + 1.1D)e1.1D fs * 4.8A.
Furthermore the transfer function from the voltage error amplifier output vc to the converter output vo can be derived from Figure 15.
s Vo (s) s z1 , := Gvc (s) = kR o s Vc (s) 1+ sp1 1+
Once the inner current loop is stabilized, the output voltage is then regulated with the outer voltage feedback loop. An equivalent circuit of current-mode Buck converter is shown in Figure 15.
where the single dominant-pole is
sp1 = 1 (R o + R oesr )Co
and the zero associated with the output capacitor ESR is
s z1 = 1 . R oesr C o
k
The dominant-pole changes with the converter output load. The controller transfer function (from the converter output vo to the voltage error amplifier output vc) is
gmh C(s) = s(C 2 + C 3 ) s s z2 , s 1+ sp2 1+
Figure 15. A simple model of current-mode buck converter The voltage transconductance error amplifier (in the SC2441) has a g m of 400A/V. C2, C 3 and R 2 of the compensation network are to be determined for stable operation with optimized load transient response. The feedback gain h and the resistor values are determined using the equations given in the "Setting the Output Voltage" section with
0.5 h= . Vo
where
sz2 = 1 R 2C 2 1 . C 2C 3 R2 C 2 + C3
and
sp2 =
The loop transfer function is then T(s)=Gvc(s)C(s).
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
P2 is a pole for suppressing high-frequency switching noise. So P2 >> Z2. To simplify design, one usually assumes that C3<C2 = gmhkR o , 2fc R oCo C2
R2 =
and
C3 = R oesr C o . R2
For example, if Vin=3.3V, V o=1.2V, I o=4A, f s=500kHz, Co=390F, Roesr=16m, one can calculate that
Ro = h= Vo = 300m , Io 0.5 = 0.42 Vo
and
k= Io = 2.60. Vc
Figure 16. Bode plots of the loop response. The resulting crossover frequency is about 49.2kHz with phase margin 90o. If the circuit noise makes the converter jitter, a larger C3 than the calculated value can be used. Effectively the converter bandwidth is reduced to reject high frequency noises. The final circuit should be checked for stability under load transients at different line voltages. The load transient also needs to be measured to ensure that the output voltage is within the specification window. Step-up Converter The step-up regulator in the SC2441 is integrated with a 1.7A power switch. Switch current sensing and ramp compensation are implemented internally. The switching frequency fs3 of the step-up regulator is twice those of the step-down controllers.
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If the converter crossover frequency is set around 1/10 of the switching frequency, f c=50kHz, the controller parameters then can be calculated.
C2 = gmhkR o 0.497nF, 2fc
use C2=0.47nF.
R2 = R oCo 150 .8k, C2
use R2=150k. It is further calculated that
RC C 3 = oesr o 4.97pF, R2
use C3=5pF. The Bode plots of the loop transfer function (magnitude and phase) are shown in Figure 16.
2005 Semtech Corp.
SC2441
POWER MANAGEMENT Applications Information (Cont.)
Given the input voltage Vin, the output voltage Vo3 and the load current Io3, the following circuit parameters are to be determined. Inductor Selection For a specified inductor current ripple (peak-to-peak) 3, the inductor value is Maximum Output Current Figure 4 shows that the boost switch current is sensed with an internal sense resistor Rs. With a current limit threshold voltage of 14mV, the maximum output current is
(1 - D 3 )14mV . R s (1 + 3 ) 2 The boost switch current limit is internally set at 1.7A. Io3,max =
L3 =
Vin VV (1 - in ) in . fs3 3Io3 Vo3 Vo3
Voltage Feedback With the internal reference voltage Vref3=1.25V, the voltage feedback gain is
h3 = Vref 3 1.25 = = 0.25. Vo3 5
If Vin = 3.3V, Vo3 = 5V and Io3 = 1A with3 = 0.3 and fs3 = 1MHz, then, L3 = 2.5H. For operation above 1MHz, Ferrite core material should be used for lower core losses and better circuit efficiency. The peak inductor current is (1+0.5*3)Io3. The saturation current rating of the selected inductor should be at least 1.2~1.5 times of the calculated peak current value. In the example above, the peak inductor current is 1.74A. Capacitor Selection Input capacitor: The input capacitance should be large : such that the input transients due to both the step-up and the step-down converters do not trip the UVLO threshold 1.59V. Since the SC2441 controls a 2-phase low input voltage step-down converter, the input capacitance is sized to handle the input ripple current of the buck converter. This is usually sufficient for the auxiliary boost converter because the input current in a boost converter is continuous. A small (< 1uF) ceramic bypass capacitor can be soldered close to the PVIN pin for high frequency filtering. Output capacitor: Unlike buck converter, pulse current is delivered to the output of a boost converter. To reduce the output ripple voltage, low ESR capacitors should be used. The output capacitor should also be able handle the output ripple current. The SC2441 is designed to use multi-layer ceramic capacitor as the sole output capacitor.
The values of the feedback resistors can be determined from the equation in "Setting the Output Voltage" section. Loop Compensation A simple small signal model for current-mode boost converter in continuous-conduction mode is shown in Figure 17.
SL 3 (I - D 3 ) I - (I - D ) 2 R 3 O3

Figure 17. Small signal model of Boost converter.
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
In Figure 17, Co3 and Resr3 are the capacitance and the ESR of the output capacitor, gm3 is the error amplifier transconductance and k3 is the current loop gain. If one specifies the loop crossover frequency f c , the compensation component values are readily calculated as Bode plots of the loop response are shown in Figure 18.
C 4 = h 3 gm3k 3 (1 - D 3 )
R4 =
R o3 f R esr 3 1 | 1- c | , 2 fz1 2fc R esr 3 + 0.5R o3
1 R Co3 (R esr 3 + o3 ) C4 2 2R esr 3 Ro3
and
C5 = C 4
with
fz1 = (1 - D 3 )2 R o3 . 2L 3
Figure 18. Typical loop transfer function Bode plot of the Boost converter.
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SC2441
POWER MANAGEMENT Applications Information (Cont.)
PC Board Layout Issues Circuit board layout is very important for the proper operation of high frequency switching power converters. A power ground plane is required to reduce ground bounces. The followings are suggested for proper layout. Power Stage 1) Separate the power ground from the signal ground. In SC2441 the power ground PGND should be tied to the source terminal of lower MOSFETs. The signal ground AGND should be tied to the negative terminal of the output capacitor (ouput return terminal). 2) Minimize the size of pulse current loop. Place the top MOSFET, the bottom MOSFET and the input capacitors close to each other with short and wide traces. In addition to the aluminum energy storage capacitors, add multi-layer ceramic (MLC) capacitors from the input to the power ground to improve high frequency bypass. 3) Reduce high frequency voltage ringing. Widen and shorten the drain and source traces of the MOSFET's to reduce stray inductances. Add a small RC snubber if necessary to reduce the high frequency ringing at the phase node. Sometimes slowing down the gate drive signal also helps in reducing the high frequency ringing at the phase node. 4) Shorten the gate driver path. Integrity of the gate drive (voltage level, leading and falling edges) is important for circuit operation and efficiency. Short and wide gate drive traces reduce trace inductances. Bond wire inductance is about 2~3nH. If the length of the PCB trace from the gate driver to the MOSFET gate is 1 inch, the trace inductance will be about 25nH. If the gate drive current is 2A with 10ns rise and falling times, the voltage drops across the bond wire and the PCB trace will be 0.6V and 5V respectively. This may slow down the switching transient of the MOSFET's. These inductances may also ring with the gate capacitance. 5) Put the decoupling capacitor for the gate drive power supplies (BST and VCC) close to the IC and power ground. Control Section 6) The frequency-setting resistor Rosc should be placed close to Pin 10. Trace length from this resistor to the analog ground should be minimized. 7) Solder the VCC decoupling capacitor next to the VCC and power ground PGND pins. 8) Place the combi-sense components away from the power circuit and close to the corresponding CS+ and CS- pins. Use X7R type ceramic capacitors for combi-sensing due to their thermal stability. 9) Use an isolated local ground plane for the controller and tie it to the negative side of output capacitor bank.
A note for Vin = 12V application Figure 21 shows an application where the input voltage is 12V. A LDO is used to provide 5V bias for SC2441. The voltages at BST1 (Pin 25) and BST2 (Pin 18) should not exceed their maximum voltage rating (20V).
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SC2441
POWER MANAGEMENT Application Information
V i : 3.3V n
VinGND
R33 J1
= V o 3: 5V / 0.5A
4 3 2 1
C11 +
R14 C7 C6+ C5 + C40 C38 R15 C1+ C2 D1 C8 1 IN PH3 VCC BST1 GDH1 FB3 COMP3 PVIN BST2 GDH2 7 8 28 18 19 R3 Q5 L2 C25 R5 R10 RCS+1 C20 R9 R12 C29 + + C10 + C9
C4+ D2 C14 + C13 + C12
C3 C34 D6 L3
C35
+
27 C17 21 R4 25 23
C18
VO1: 1.2V/4A
C22 C24
Q1 L1
VO2: 2.5V/1A
C26
C23
D7
Q2
R8
VO1GND
C21 R11 RCS+2
R6 R13
22 24 26 4
GDL1 PGND VPN1 CS1+ CS1FB1 COMP1
GDL2
20
R7
Q6
D5
C19
VPN2 CS2+ CS2FB2 COMP2
2 16 15 14 13 C27 C30 R18
C39 RCS-2 C28 R19 C31
5 11 12
VO2GND
RCS-1
R16
R17
10 R20
Rosc
SYNC SS1/EN1 U1 SS2/EN2
6 3 17 C33 C32 R30
9
GND
SC2441
Figure 19. Two independent buck converters with auxiliary boost
VinGND
Vin: 3.3V
R 33 J1
= Vo3: 5V/0.5A
4 3 2 1
C 11 C7 + C6+ C5 + C4 + D2 C 14 + C 13 + C 12 27 C 17 21 25 Q1 L1 R4 23 C3 C 34 D6 1 + IN P H3 VC C BST1 G DH1 F B3 COMP3 PVIN BST2 G DH2 7 8 28 18 19 R3 Q5 R 12 C 29 L3 C 40 C 35 C 38
R 14
R 15 C1 + C2 D1 C8 + + C 10 + C9
C 18
VO1: 1.2V/20A
C 22 C 24
L2 C 25 R5 R 10 R CS +1 C 20 C 26
VO1
C 23
D7 Q4 R 13
Q2
R8
VO1GND
C 21 R 11 R CS +2
22 24 26 4
R6
GD L1 P GN D VPN1 CS1+ CS1F B1 COMP1
GD L2
20
R7
Q6
Q8
D5
C 19
VPN2 CS2+ CS2F B2 COMP2
2 16 15 14 13
C 39 R CS -2 C 28 R 19 C 31
5 11 12
VO1GND
R CS -1
R 16
10 R 20 9
Rosc
S YN C SS1 /E N1 U1 SS2 /E N2
6 3 17 C 33 C 32
GN D
SC2441
Figure 20. Dual-phase single output buck (current sharing) with single boost
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IN 8 FB 7
SC LDO
SENSE
1 OUT
2
3
SHDN
4
GND
TAP 6 ERRORB 5
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Vin: 12V
R12
POWER MANAGEMENT Typical Application Circuit
VinGND
C7 + + C4+ C35 C34 D2 1 IN COMP3 PH3 VCC BST1 R3 19 L2 C25 C23 22 GDL1 PGND VPN1 CS1+ CS1FB1 COMP1 CS2FB2 COMP2 CS2+ 16 15 14 13 C27 C30 10 R20 9 GND 6 Rosc SYNC 3 SS1/EN1 U1 17 SS2/EN2 C33 C32 R18 RCS-1 VPN2 2 RCS+1 GDL2 24 R13 26 4 5 11 C28 12 R19 C31 20 R10 R9 R6 D7 Q2 R8 R7 Q6 D5 C19 R5 C20 C26 Q5 GDH1 GDH2 BST2 18 PVIN 28 C18 8 FB3 27 21 C17 25 Q1 23 R4 7 + C2 D1 C8 + C10 + C9 C3 C1+ C6+ C38 C5
C14
C13
C12
+
+
+
Figure 21. Dual output Buck with 12V input
R30
29
SC2441
VO2: 2.5V/1A
VO1: 1.2V/4A
L1
C22
C24
C21
VO1GND
R11
RCS+2
VO2GND
RCS-2
R16
R17
SC2441
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SC2441
POWER MANAGEMENT Evaluation Board - Bill of Materials
R ef 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Qty 1 3 1 1 2 2 1 1 2 3 1 1 1 1 1 2 1 1 2 1 1 1 1 Reference C7 C2,C3,C6 C11 C 12 C17,C18 C19,C23 C 20 C 21 C22,C25 C24,C26,C34 C 27 C 28 C 29 C 30 C 31 C32,C33 C 35 C 40 D1,D2 D6 L1 L2 L3 Part Number/Value 150uF, 6.3V, 30mohm, Alum. or OS-CON 22uF, 6.3V, X5R, Ceramic 1210 47uF, 6.3V, X5R, Ceramic 100uF, 6.3V, X5R, Ceramic 0.33uF, 50V, X5R (or X7R) 1206 2.2nF, X5R, Ceramic, 0805 22nF, X5R, Ceramic, 0805 10nF, 16V, X5R, Ceramic, 0805 22uF, 6.3,V X5R, Ceramic, 1210 10uF, 6.3V,X5R, Ceramic, 1206 10pF, X5R, Ceramic, 0805 10pF, Ceramic, 0805 1nF, 16V, X5R, Ceramic, 0805 0.22nF, X5R, Ceramic, 0805 0.47nF, X5R, Ceramic, 0805 100nF, X5R, Ceramic, 0805 1uF, 16V, X5R, Ceramic, 0805 100pF, 16V, X5R, Ceramic, 0805 40V, 1A, Schottky 40V, 3A, B340A SMA, Shottky, SOD-123 1.8uH, 14A, 3.3mohm 6.8uH, 1.5A, 52mohm 9uH, 1.9A, 57mohm Manufacturer Sanyo P/N: 6SP150M Taiyo Yuden P/N: YMK325BJ226MM TDK P/N: C3225X5R0J476MJ TDK P/N: C3225X5R0J107M Vishay P/N: VJ1206Y334KXAAT Any Any Any Taiyo Yuden P/N: YMK325BJ226MM TDK P/N: C3216X5R0J106MT Any Any Any Any Any Any Any Any General Semi P/N: 1N5819M, MELF Motorola P/N: MBRS140T3 Diode Inc. Panasonic P/N: ETQP6F1R8BFA Panasonic P/N: ELL6SH6R8M Pulse Eng. P/N: P1167.123T
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SC2441
POWER MANAGEMENT Evaluation Board - Bill of Materials
R ef 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Qty 2 1 1 1 1 4 2 1 2 2 1 1 1 1 1 1 1 1 1 Reference (Q1,Q2), (Q5,Q6) RCS+1 RCS+2 RCS-1 RCS-2 R3,R4,R7,R8 R5,R6 R9 R10,R13 R11,R14 R12 R15 R16 R17 R18 R19 R20 R33 U1 Part Number/Value 12V, 11.8A, 17mohm, Power p a ck 2K , 0805 5.1K, 0805 100 Ohm, 0805 10K , 0805 1 Ohm 5%, 0805 1 5 k, 0 8 0 5 3.92K, 1%, 0805 5.1 Ohm, 0805 4.02K, 1%, 0805 33.2K, 1%, 0805 1.43K, 1%. 0805 3.01K, 1%. 0805 1.02K, 1%. 0805 301K , 0805 150K , 0805 47.5K, 1%. 0805 0 Ohm, 0805 S C 2441 Manufacturer Vishay P/N: Si7940DP Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Semtech Corp.
* Dual output Buck with single Boost.
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SC2441
POWER MANAGEMENT Typical Characteristics
Typical waveforms in the evaluation circuit board No load start up
Channel 1: Vo=1.2V @ 4A Overload protection Output shorted
Load transient response Loading: 0.4A to 3.6A to 0.4A, 2.5A/uS
output short persists
Shut down
Output short removed
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SC2441
POWER MANAGEMENT Typical Characteristics (Cont.)
Typical waveforms in the evaluation circuit board Full load start up
Channel 2: Vo=2.5V @ 1A Overload protection Output shorted
Load transient response Loading: 0.1A to 0.9A to 0.1A at 2.5A/uS
Output short persists
Shut down
Output short removed
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SC2441
POWER MANAGEMENT Typical Characteristics (Cont.)
Typical waveforms in the evaluation circuit board Channel 3: Vo=5V @ 0.4A Start up
Load transient response Loading: 0.04A to 0.36A to 0.04A at 2.5A/uS
Shut down
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SC2441
POWER MANAGEMENT Outline Drawing - TSSOP-28
Land Pattern - TSSOP-28
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804
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